This invention relates generally to the design and implementation of integrated circuits. More particularly, this invention relates to a technique for interleaving a signal carry chain in an integrated circuit.
In the increasingly competitive market of integrated circuits, there is an ongoing need to improve the design and implementation of integrated circuits. Improving the design and implementation of integrated circuits in turn improves resource utilization and circuit performance. One way to improve the design and implementation of integrated circuits is to redesign the signal carry structures in integrated circuits, such as the signal carry structures in programmable logic devices.
Many integrated circuit designs today comprise bussing schemes between two busses of different sizes. In such circuits, performance degradation occurs in the bussing interconnect and/or arithmetic structures. Performance degradation occurs because arithmetic structures are constrained from carry chains that require a strictly bit-sequential ordering of the structure. Interconnect between two buses of different sizes may benefit by a different bit ordering, such as an interleaved order. For example, when communicating between a 32-bit bus and a 16-bit bus, it is common to interconnect both the upper and lower 16-bit words of the 32-bit bus to the 16-bit bus. That is, both 32-bit bus bits xe2x80x9c31xe2x80x9d and xe2x80x9c15xe2x80x9d interconnect to 16-bit bus bit xe2x80x9c15xe2x80x9d, both 32-bit bus bits xe2x80x9c30xe2x80x9d and xe2x80x9c14xe2x80x9d interconnect to 16-bit bus bit xe2x80x9c14xe2x80x9d, and so on. Given this interleaved relationship, it is desirable to arrange the bus in an interleaved fashion, known as an interleaved bus.
In contrast, contemporary macro generators, whether programmable or standard cell devices, generate arithmetic structures that are bit-sequential. Namely, 32-bit objects are generated from bit D31 down to bit D0, and 16-bit objects are generated from bit D15 down to bit D0. Such sequentially arranged structures do not expediently permit the interleaved bus scheme. To accommodate such an interleaved bus, data structures must be generated in a like-wise interleaved arrangement. However, in order to accommodate such interleaved data structures, programmable devices have to contain an interleaved carry structure.
Accordingly, it would be highly desirable to provide an improved technique for interleaving a signal carry chain in an integrated circuit.
An interleaved signal carry structure includes a first signal line and a second signal line forming a first bus. A third signal line and a fourth signal line form a second bus. A first set of carry function generators are positioned between the first signal line and the third signal line. Each carry function generator in the first set of carry function generators receives input from both the first signal line and the third signal line. Carry-in signal lines are attached to the first set of carry function generators. A second set of carry function generators are positioned between the second signal line and the fourth signal line. Each carry function generator in the second set of carry function generators receives input from both the second signal line and the fourth signal line. Intermediate carry signal lines are positioned between the first set of carry function generators and the second set of carry function generators. Carry out signal lines are attached to the second set of carry function generators. A first vertical carry chain comprises a first carry function generator from the first set of carry function generators and a first carry function generator from the second set of carry function generators. A second vertical carry chain comprises a second carry function generator from the first set of carry function generators and a second carry function generator from the second set of carry function generators.
An interleaved signal carry structure includes a first signal line and a second signal line forming a first bus. A third signal line and a fourth signal line form a second bus. A first set of carry function generators are positioned between the first signal line and the third signal line. Each carry function generator in the first set of carry function generators receives input from the first signal line and the third signal line. A set of carry-in signal lines are attached to a first end of each of the first set of carry function generators. A first set of logic elements is attached to a second end of each of the first set of carry function generators. The first set of logic elements is attached selectively at a second end to the first signal line and the third signal line. A second set of carry function generators are positioned between the second signal line and the fourth signal line. Each carry function generator in the second set of carry function generators receives inputs from the second signal line and the fourth signal line. A set of intermediate carry signal lines are attached between a third end of each of the first set of carry function generators and a first end of each of the second set of carry function generators. A second set of logic elements is attached at a first end to a second end of each of the second set of carry function generators. The second set of logic elements are attach selectively at a second end to the second signal line and the fourth signal line. A set of carry out signal lines attached to a third end of each of the second set of carry function generators. A first vertical carry chain comprises a first carry function generator from the first set of carry function generators and a first carry function generator from the second set of carry function generators. A second vertical carry chain comprises a second carry function generator from the first set of carry function generators and a second carry function generator from the second set of carry function generators.
Various embodiments of this invention provide signal carry structures that decrease routing resource consumption, thus, enhancing routing efficiency in programmable logic devices.